The present invention relates to a process of fabricating a circuitized structure, e.g. a circuit board, laminated chip carrier or card, by combining laminate technology with substrate technology. Specifically, by combining these two technologies in a single process, as is done herein, a circuitized structure having fine features and a high wire density is formed.
Conventional printed circuit cards and boards utilize drilled and plated through holes for communication between opposite sides and intermediate layers of the board to wiring formed on both sides of the board. Frequently, the plated through holes will also receive pins for the connection of various types of circuit components. It is usually required that the plated through holes be able to act as a soldering socket for a module and that requires that they be fairly large and that a solderable ring or land of metal be provided around the plated through holes on the surface of the circuit board so as to allow for soldered connections.
This type of structure dictates that a large amount of card or board space cannot be used for point to point wiring since the wiring must be done in the spaces between the holes, leaving room between the individual wire lines and between the wire lines and the solder rings.
Recently, there has been introduced surface modules and thin film chip wiring devices that do not have pins but have other types of connection pads. With this type of structure the space necessary for the holes can be reduced somewhat; nevertheless even with this technology a significant amount of space is used by the holes which is not available for surface wiring.
Different techniques have been suggested for various types of wire interconnection wherein plated through holes are present on the board. For example, U.S. Pat. No. 3,356,786 describes a technique where conducting lines can be provided which extend across various openings or holes. This technique, however, has many limitations both in the structures available and the utilization of the holes. Other patents that describe techniques for increasing somewhat the wiring density, are U.S. Pat. Nos. 4,554,405, 4,581,679, 4,535,388, 4,598,166, 4,179,800. None of these references combine laminate technology with substrate technology. Thus, the prior art processes cannot readily achieve fine line features on the circuitized substrate using a single process.
In view of the drawbacks mentioned hereinabove, there is a continued need to develope new processes for improving the wiring density of circuitized structures.
One object of the present invention is to provide a process of fabricating a circuitized structure having multiple inner planes of a laminate and a high wiring density.
Another object of the present invention is to provide a process which fabricates a circuitized structure containing fine line circuitry.
A further object of the present invention is to provide a process of fabricating a circuitized structure having uniform line impedance across multiple parts of connected ground planes providing a system which has reduced electronic noise.
These as well as other objects are achieved by the present process which combines laminate technology and substrate technology in a single process. Specifically, the present invention relates to a process of fabricating a circuitized structure, e.g. a circuit board, laminated chip carrier or card, having fine line circuitry thereon. More specifically, the present invention comprises the steps of:
(a) applying a dielectric film to at least one surface of an organic substrate having circuity thereon;
(b) forming microvias in selective portions of said dielectric film;
(c) sputtering a metal seed layer on said dielectric film and in said microvias;
(d) plating a metallic layer on said metal seed layer; and
(e) forming outer circuitry on said plated metallic layer.
Preferred dielectric films that are employed in the present invention include, but are not limited to, dielectric films that contain a photoimageable layer or dielectric films which are capable of forming microvias when exposed to laser irradiation.
In one embodiment wherein a dielectric film containing a photoimageable layer is employed, the process of the present invention comprises the steps of:
(a) providing a dielectric film having a photoimageable layer therein;
(b) laminating said photoimageable layer of said dielectric film to at least one surface of an organic substrate having circuitry thereon;
(c) exposing said photoimageable layer of said dielectric film to a pattern of radiation to selectively harden portions of said photoimageable layer;
(d) providing microvias in said photoimageable layer which is not harden by step (c);
(e) curing said structure providing in step (d);
(f) sputtering a metal seed layer on said cured structure and in said microvias;
(g) plating a metallic layer on said metal seed layer; and
(h) forming outer circuitry from said metallic layer provided in step (g).
On the other hand, when a dielectric film that is capable of forming microvias when exposed to laser irradiation is employed in the present invention, the following steps are utilized:
(a) applying a dielectric film that is capable of forming microvias upon exposure to laser energy to at least one surface of an organic substrate having circuitry thereon;
(b) forming microvias in selective portions of said dielectric film by irradiating the same with laser energy;
(c) cleaning said microvias to remove any laser debris;
(d) sputtering a metal seed layer on said dielectric film and in said microvias;
(e) plating a metallic layer on said metal seed layer; and
(f) forming outer circuitry from said metallic layer provided in step (e).
No matter which of the above processes is employed in the present invention, it is emphasized that a seed layer containing a metal such as Cr, Cu and the like is sputtered on to the surface of the dielectric film and in the microvias. By xe2x80x9cseed layerxe2x80x9d it is meant that a very thin metal layer of less than about 2000 xc3x85 is sputtered on the surface of said dielectric film and in said microvias. This seed layer is distinguishable from a full metal layer wherein the thickness is typically greater than about 0.2 mils.